Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET or MOS), in which a gate is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-channel and p-channel (NMOS and PMOS) transistors are used to fabricate logic and other circuitry.
The source and drain are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel. A gate structure is formed above the channel, having a gate dielectric formed over the channel and a gate electrode above the gate dielectric. The gate dielectric is an insulator material, which prevents large currents from flowing into the channel when a voltage is applied to the gate electrode, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Conventional MOS transistors typically include a gate dielectric formed by depositing or growing silicon dioxide (SiO2) or silicon oxynitride (SiON) over a silicon wafer surface, with doped polysilicon formed over the SiO2 or SiON to act as the gate electrode.
Continuing trends in semiconductor device manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface. However, there are electrical and physical limitations on the extent to which the thickness of SiO2 or SiON gate dielectrics can be reduced. For example, leakage in very thin SiO2 or SiON gate dielectrics is dominated by tunneling currents resulting from direct tunneling through the thin gate oxide. In addition, thin SiO2 or SiON gate dielectric layers provide a poor diffusion barrier to dopants, for example, and may allow high boron dopant penetration from the poly silicon electrode into the underlying channel region of the silicon substrate during fabrication of the source/drain regions.
Recent MOS transistor scaling efforts have accordingly focused on high-k dielectric materials having dielectric constants greater than that of SiO2 (e.g., greater than about 3.9) and thus can be formed in a thicker layer than SiO2 or SiON, and yet produce equivalent field effect performance. The relative electrical performance of such high-k dielectric materials is often expressed as equivalent oxide thickness (EOT), because the high-k material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2 or SiON. Since the dielectric constant “k” is higher than silicon dioxide, a thicker high-k dielectric layer can be employed to mitigate tunneling leakage currents, while still achieving the equivalent electrical performance of a thinner layer of thermally grown SiO2 or SiON.
The performance of the resulting MOS transistors is dependent upon the high-k gate dielectric material, including the bulk high-k material and on a thickness or equivalent oxide thickness of deposited material. Unlike SiO2 or SiON, which may be formed by thermal oxidation (growth process), high-k dielectrics are typically deposited over the semiconductor substrate using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or other deposition processes. While the macroscopic composition of these materials may be controlled to a certain extent during such deposition processes, stoichiometric composition variations within the film may vary and thus degrade device performance.